The present invention relates to a semiconductor memory device employing a capacitor insulating film provided by a ferroelectric thin film or a highly dielectric thin film.
The conventional nonvolatile memories of EPROM (Erasable Programable Read Only Memory), EEPROM (Electrically Erasable Programmable Read Only Memory), flash memory and so on have the same read time as that of DRAM (Dynamic Random Access Memory); however, they have a long write time, for which no high-speed operation can be expected. In contrast to this, the ferroelectric memory that is a nonvolatile memory employing a ferroelectric capacitor and has the same read and write performances as those of DRAM is the nonvolatile memory with which a high-speed operation can be expected.
In regard to the device structure of this ferroelectric memory, one ferroelectric capacitor and one select transistor constitute one cell.
As an electrode material of the ferroelectric capacitor, platinum has widely been used for both the upper electrode and the lower electrode for such a reason that it has a resistivity to a high-temperature oxidative atmosphere for crystallizing the ferroelectric material. As a ferroelectric material to be used for the ferroelectric capacitor, attention is focused on SrBi.sub.2 Ta.sub.2 O.sub.9 (SBT) and Bi.sub.4 Ti.sub.3 O.sub.12 (BIT) that have excellent fatigue properties and are able to be operated at low voltage as compared with PbZr.sub.x Ti.sub.1-x O.sub.3 (PZT) having been examined to the detail, and the former substances are under elaborate examination.
As a method for forming the above ferroelectric thin film, there are a MOD (Metal Organic Deposition) method, a sol-gel method, a MOCVD (Metal Organic Chemical Vapor Deposition) method, a sputtering method and so on. According to any one of the film forming methods, the oxide ferroelectric film must be crystallized by heat treatment in an oxidative atmosphere at a high temperature of about 600 to 800.degree. C.
When forming a stacked type capacitor of such an oxide ferroelectric material, it is a general practice to provide a first interlayer insulating film on a MOS (Metal-Oxide Semiconductor) transistor of a select transistor or the like, laminate a lower electrode and a ferroelectric thin film in this order, process the integrated body into a desired shape by the dry etching technique, cover it with a second interlayer insulating film of an ozone TEOS film formed by CVD (Chemical Vapor Deposition) for decomposing the vapor of a liquid TEOS (Tetraethoxysilane) by ozone, open the upper portion of a capacitor and make contact with the upper electrode. Further, a third interlayer insulating film is formed on it and other interconnections are provided.
On the other hand, in order to increase the capacitance of the capacitor in correspondence with the high integration of DRAMs, oxide highly dielectric materials such as tantalum oxide (Ta.sub.2 O.sub.5), strontium titanate (SrTiO.sub.3), barium strontium titanate ((Ba, Sr)TiO.sub.3) are about to be applied to highly integrated DRAMs of a scale of 256 megabits to a scale of not smaller than gigabits in future, and they are elaborately examined. When forming a stack type capacitor with such a highly dielectric material, a method similar to that of the ferroelectric material is used.
A ferroelectric capacitor is formed by the aforementioned method, and this is followed by the lamination of platinum, titanium and titanium nitride stacked in this order as the upper electrode and the processing of the upper electrode into a drive line shape. Further, a third interlayer insulating film is formed, and it is desirable to use a CVD film (plasma TEOS film) obtained through the decomposition with TEOS by the PECVD (plasma assist CVD) as an interlayer insulating film material for it.
The above is because the ozone TEOS film, which is often used by other methods, has a significant groundwork dependency, and as shown in FIG. 2, a variation occurs in the formed film thicknesses A, B and C. Therefore, a difference in level increases, consequently making the subsequent fine processing become difficult. Furthermore, this film has a great film stress. Therefore, when the film is deposited to a thickness not smaller than a specified film thickness, the film sometimes comes to have cracks or exfoliates. The thicknesses A, C are those on metal-wirings, while the thickness B is that on a substrate.
As another generic method, there can be enumerated a thermal decomposition CVD method using silane or the like as a material. According to this method, although there remains relatively little hydrogen content after film formation, it cannot be used because it forms a film in a high-temperature reductive atmosphere exceeding the heat resistance of the ferroelectric film, lower electrode and so on.
However, the plasma TEOS film is also formed in a reductive atmosphere containing hydrogen, and the hydrogen diffuses through the upper electrode in forming the plasma TEOS film, consequently reducing the surface of the ferroelectric material that is also an oxide. Furthermore, the plasma TEOS film obtained after film formation contains a very small quantity of hydrogen, and therefore, the hydrogen separates from the plasma TEOS film and diffuses every time annealing is executed after film formation. This consequently causes a problem that the ferroelectric film is gradually reduced to disadvantageously deteriorate the ferroelectric characteristic and increase the capacitor leak current.
As a further serious problem, it is required to perform annealing in a hydrogen atmosphere for compensating for the defect in the substrate in a stage in which the device fabrication is completed. Also in this case, hydrogen is diffused in the film similar to the aforementioned case, disadvantageously deteriorating the ferroelectric film. In order to solve this problem, there has been an attempt at using an oxide electrode of IrO.sub.2, RuO.sub.2, RhO.sub.2 or the like as an upper electrode for suppressing the influence of hydrogen.
Furthermore, a technique using an alloy of platinum and rhodium as an upper electrode is disclosed in the document of Japanese Patent Laid-Open Publication No. HEI 5-343251, and this method will be described with reference to FIG. 10.
First, an alloy film 101 of platinum and rhodium is formed by the DC sputtering method on a first silicon oxide film 102 formed on an n-type silicon substrate. Next, the alloy film 101 of platinum and rhodium is etched by the dry etching method by means of a halogen-based gas using a photoresist as a mask, and thereafter the photoresist is removed, thereby forming a lower electrode.
Next, PZT that is a ferroelectric film is formed by the RF sputtering method and thereafter etched through a photo-process similar to the lower electrode, thereby forming a dielectric film 103. Next, an alloy film of platinum and rhodium is formed by the DC sputtering method, and thereafter an alloy film of platinum and rhodium is etched by the dry etching method by means of a halogen-based gas using a photoresist as a mask similar to the formation of the lower electrode, thereby forming an upper electrode 104. Subsequently, a second silicon oxide film 106 is formed and thereafter a contact hole and an Al interconnection layer 105 are formed, thereby forming a ferroelectric memory cell having the cross-section shape shown in FIG. 10.
However, if the oxide electrode of IrO.sub.2, RuO.sub.2, RhO.sub.2 or the like is used, there have been conversely caused the asymmetry of a hysteresis loop characteristic of the dielectric material representing a correlation between a polarization value and an application electric field as well as a deterioration such as an increase in leak current density. Furthermore, if the oxide electrode of IrO.sub.2, RuO.sub.2, RhO.sub.2 or the like is used, the morphology of the electrode surface becomes worse, and particularly when it is used for the lower electrode, there is caused a problem that the barrier metal is oxidized to increase the leak current density.
Although the above has described the problems in the case of the ferroelectric capacitor, there has been the problem that the diffusion of hydrogen from the interlayer insulating film and the heat-treatment atmosphere occurs even in forming a capacitor employing a highly dielectric material of an oxide and the highly dielectric film is reduced by hydrogen activated with platinum served as a catalyzer, consequently lowering the dielectric constant in terms of practical effect.
Furthermore, when forming an alloy film of platinum and rhodium as an upper electrode of the ferroelectric capacitor, the characteristics of the ferroelectric film deteriorate since the alloy film of platinum and rhodium has the platinum crystallinity for allowing hydrogen to easily pass through it. Furthermore, the alloy film of platinum and rhodium is oxidized to cause a volume expansion in forming the interlayer insulating film and so on, possibility generating an exfoliation from a portion having a weak adherence.